1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a DRAM and a manufacturing method thereof.
2. Description of the Prior Art
Some DRAMs (Dynamic Random Access Memories) as volatile semiconductor memories have a CUB (Capacitor Under Bit-line) structure in which a capacitor is formed before a bit line (see Japanese Patent Application Laid Open Publication No. 10-242422, for example). FIG. 5A is a top view showing a conventional DRAM having a CUB structure. FIG. 5B is a sectional view taken along the line Vb-Vb in FIG. 5A, and FIG. 5C is a sectional view taken along the line Vc-Vc in FIG. 5A.
As shown in FIG. 5B and FIG. 5C, the conventional DRAM includes: source/drain regions 114 of a MOS (Metal Oxide Semiconductor) transistor formed in a silicon substrate 111; a gate insulating film 113 formed on the substrate 111 between the source/drain regions 114 when viewed in plan; a gate electrode 123 formed on the gate insulating film 113; a first interlayer insulting film 115 formed on the substrate 111, the source/drain regions 114, and the gate electrode 123; and a liner film 122 formed on the first interlayer insulating film 115. The conventional DRAM further includes: a second interlayer insulating film 117 formed on the liner film 122 and having a trench; a capacitor composed of a storage node electrode 118, a capacitance insulating film 119, and a plate electrode 120 which are formed on one of the source/drain regions 114 along the inner wall of the trench in this order from below; a third interlayer insulating film 128 formed on the plate electrode 120 and the second interlayer insulating film 117; and a bit line 124 formed on the third interlayer insulating film 128 and extending in the gate length direction of the MOS transistor.
Moreover, the conventional DRAM includes: a first conductive plug 116a passing through the first interlayer insulating film 115 and connecting one of the source/drain regions 114 and the storage node electrode 118; a second conductive plug 116b passing through the first interlayer insulating film 115 and connected to the other source/drain region 114 that is not connected to the first conductive plug 116a; and a third conductive plug 121 passing through the liner film 122, the second interlayer insulating film 117, and the third interlayer insulating film 128 on the second conductive plug 116b and connecting the second conductive plug 116b and the bit line 124. The central axis of the third conductive plug 121 agrees with the central axis of the second conductive plug 116b. Wherein, the MOS transistor includes a plurality of MOS transistors separated from each other by an element isolation insulting film 112 formed in the substrate 111. Each MOS transistor and one capacitor connected thereto compose one memory cell.
As shown in FIG. 5A, each third conductive plug 121 is surrounded by a hole 125 of the plate electrode 120 when viewed in plan and is arranged in such a fashion that the central axis thereof is intersected with an extension connecting the major axes at the bottom of the storage node electrodes 118 formed on the respective sides of the third conductive plug 121. Though the capacitance insulating film 119, the plate electrode 120, the third interlayer insulating film 128, and the bit line 124 are not shown in FIG. 5A, the plate electrodes 120 are formed integrally and entirely above the substrate 111 and form the holes 125 surrounding the third conductive plugs 121.
As described above, the conventional DRAM shown in FIG. 5 includes capacitors having a 3-D structure, so that the sufficient capacitance of the capacitors can be secured with the projection area reduced, leading to reduction in cell area.